On 02/10, Georgi Djakov wrote: > Hi Lina, > Thanks for reviewing. > > On 02/10/2016 12:21 AM, Lina Iyer wrote: > > On Tue, Feb 09 2016 at 06:13 -0700, Georgi Djakov wrote: > [..] > >> +#define SPM_REG_STS_1 0x10 > >> +#define SPM_REG_VCTL 0x14 > >> +#define SPM_REG_PMIC_DATA_0 0x28 > >> +#define SPM_REG_PMIC_DATA_1 0x2c > >> +#define SPM_REG_RST 0x30 > >> + > > These register offsets are SoC specific. You may want to follow the model > > of drivers/soc/qcom/spm.c in getting register offsets. > > > > While I see that you are only supporting APQ8064 with this patch, you > > probably would want to think a bit far ahead. To support any other QCOM > > SoC, you would need extensive changes. > > > > The purpose of this patch it to add support for 8064. Supporting other > SoCs requires just read/writing at different offsets. To handle this we > can convert the above defines to a table containing the offsets for each > SoC. I don't think these are extensive changes or do i miss something? >
In some designs we have to talk to the PMIC with SPMI transactions to change the mode depending on the voltages. How do we plan to handle that case where the regulator control is split between two busses, SPMI and MMIO? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
