On Wed, Feb 10, 2016 at 01:26:21PM -0600, [email protected] wrote: > From: Thor Thayer <[email protected]> > > Adding L2 Cache and On-Chip RAM EDAC support for the > Altera SoCs using the EDAC device model. The SDRAM > controller is using the Memory Controller model. > > Each type of ECC is individually configurable.
All 4 applied, thanks.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
