Hi Dinh, [auto build test WARNING on clk/clk-next] [also build test WARNING on v4.5-rc5 next-20160222] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/dinguyen-opensource-altera-com/clk-socfpga-allow-for-multiple-parents-on-Arria10-periph-clocks/20160223-043710 base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next config: arm-multi_v7_defconfig (attached as .config) reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=arm All warnings (new ones prefixed by >>): drivers/clk/socfpga/clk-periph-a10.c: In function '__socfpga_periph_init': >> drivers/clk/socfpga/clk-periph-a10.c:113:20: warning: assignment from >> incompatible pointer type init.parent_names = &parent_name; ^ vim +113 drivers/clk/socfpga/clk-periph-a10.c 5343325f Dinh Nguyen 2015-05-19 97 periph_clk->div_reg = NULL; 5343325f Dinh Nguyen 2015-05-19 98 } 5343325f Dinh Nguyen 2015-05-19 99 5343325f Dinh Nguyen 2015-05-19 100 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 5343325f Dinh Nguyen 2015-05-19 101 if (rc) 5343325f Dinh Nguyen 2015-05-19 102 periph_clk->fixed_div = 0; 5343325f Dinh Nguyen 2015-05-19 103 else 5343325f Dinh Nguyen 2015-05-19 104 periph_clk->fixed_div = fixed_div; 5343325f Dinh Nguyen 2015-05-19 105 5343325f Dinh Nguyen 2015-05-19 106 of_property_read_string(node, "clock-output-names", &clk_name); 5343325f Dinh Nguyen 2015-05-19 107 5343325f Dinh Nguyen 2015-05-19 108 init.name = clk_name; 5343325f Dinh Nguyen 2015-05-19 109 init.ops = ops; 5343325f Dinh Nguyen 2015-05-19 110 init.flags = 0; 5343325f Dinh Nguyen 2015-05-19 111 aaf2a8b5 Dinh Nguyen 2016-02-22 112 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); 5343325f Dinh Nguyen 2015-05-19 @113 init.parent_names = &parent_name; 5343325f Dinh Nguyen 2015-05-19 114 5343325f Dinh Nguyen 2015-05-19 115 periph_clk->hw.hw.init = &init; 5343325f Dinh Nguyen 2015-05-19 116 5343325f Dinh Nguyen 2015-05-19 117 clk = clk_register(NULL, &periph_clk->hw.hw); 5343325f Dinh Nguyen 2015-05-19 118 if (WARN_ON(IS_ERR(clk))) { 5343325f Dinh Nguyen 2015-05-19 119 kfree(periph_clk); 5343325f Dinh Nguyen 2015-05-19 120 return; 5343325f Dinh Nguyen 2015-05-19 121 } :::::: The code at line 113 was first introduced by commit :::::: 5343325ff3dd299f459fa9dacbd95dca5c9bf215 clk: socfpga: add a clock driver for the Arria 10 platform :::::: TO: Dinh Nguyen <dingu...@opensource.altera.com> :::::: CC: Stephen Boyd <sb...@codeaurora.org> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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