Dan Williams <dan.j.willi...@intel.com> writes: > On Tue, Feb 23, 2016 at 4:26 AM, Ard Biesheuvel > <ard.biesheu...@linaro.org> wrote: >> On 23 February 2016 at 13:03, Ard Biesheuvel <ard.biesheu...@linaro.org> >> wrote: >>> On 23 February 2016 at 12:58, Russell King - ARM Linux >>> <li...@arm.linux.org.uk> wrote: >>>> On Mon, Feb 22, 2016 at 09:35:24PM +0100, Ard Biesheuvel wrote: >> OK, I see what you mean. I find it unfortunate that ioremap_cache() >> instances are blindly being replaced with memremap(), and I wonder if >> this wasted test by and/or cc'ed to people who can actually test this >> driver. Dan?
Actually I have the hardware to test it. And I also know what is behind : - it's a CFI NOR based memory - these are Intel StrataFlash 28F128J3A chips - as a CFI memory it is mapped on the system bus - from a read perspective, it behaves like a normal memory - but once the first write reaches the CFI, everything changes (the address space layout doesn't have the same meaning, be that becoming a status code or something else). In these conditions reordering of writes versus reads, merging reads after a write or coalescing writes is a recipe for disaster. All of this to say I can make a small discrete number of tests (less than 10 write or erase ones to preserve the precious NOR). Cheers. -- Robert