From: Borislav Petkov <[email protected]> Hi,
this adds support for the upcoming AMD Scalable MCA error decoding scheme to Linux (F17h stuff) (patch 2). The rest is cleanups and clarifications. Patches ontop of tip/ras/core. Aravind Gopalakrishnan (5): x86/mce: Move MCx_CONFIG MSR definitions x86/mce/AMD, EDAC: Enable error decoding of Scalable MCA errors x86/mce/AMD: Fix logic to obtain block address x86/mce: Clarify comments regarding deferred error x86/mce/AMD: Document some functionality arch/x86/include/asm/amd_nb.h | 26 ++- arch/x86/include/asm/mce.h | 69 +++++++- arch/x86/include/asm/msr-index.h | 4 - arch/x86/kernel/cpu/mcheck/mce_amd.c | 120 +++++++++---- drivers/edac/mce_amd.c | 335 ++++++++++++++++++++++++++++++++++- 5 files changed, 503 insertions(+), 51 deletions(-) -- 2.3.5
