On Thursday 31 March 2016 10:41:24, Linus Walleij wrote: > On Wed, Mar 23, 2016 at 6:01 PM, Alexander Stein > > <[email protected]> wrote: > > The interrupt for the corresponding pin is configured to trigger when the > > pin state changes compared to a preconfigured state (Bit set in INTCON). > > This state is set by setting/clearing the bit in DEFVAL. > > In the interrupt handler we need also to check if the bit in INTCON is set > > for level triggered interrupts. > > > > Signed-off-by: Alexander Stein <[email protected]> > > Patch applied. > > I'm a bit concerned that you now support both edge and level trigged > IRQs but this driver is using handle_simple_irq() in the > gpiochip_irqchip_add() call. I guess it "just works" because > the hardware will latch the edge IRQ and clear it when reading the > status register.
>From the reference manual: > The INTCAP register captures the GPIO port value at > the time the interrupt occurred. The register is ‘read > only’ and is updated only when an interrupt occurs. The > register will remain unchanged until the interrupt is > cleared via a read of INTCAP or GPIO. So, i guess you're right. Although currently I don't know why handle_simple_irq would not work if this would not be the case. > I guess you have tested it with both edge and level IRQs? Yep, I have buttons and a PCA9555 added to MCP23S17. Buttons are gpio-keys, so rising and falling edge interrupts and PCA9555 uses low level interrupts. See this excerpt from /proc/interrupts: 79: 0 2 gpio-mcp23xxx 8 Edge Digital In 0 84: 0 4 gpio-mcp23xxx 13 Level 0-0024 Best regards, Alexander
