On 03/23/2016 03:05 PM, Matthew McClintock wrote:
For certain parts and some versions of TZ, TZ will reset the chip
when a BARK is triggered even though it was not configured here. So
by default let's configure this BARK time as well.

Signed-off-by: Matthew McClintock <[email protected]>

Reviewed-by: Guenter Roeck <[email protected]>

---
  drivers/watchdog/qcom-wdt.c | 5 +++++
  1 file changed, 5 insertions(+)

diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index e46f18d..53f57c3 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -22,18 +22,21 @@
  enum wdt_reg {
        WDT_RST,
        WDT_EN,
+       WDT_BARK_TIME,
        WDT_BITE_TIME,
  };

  static const u32 reg_offset_data_apcs_tmr[] = {
        [WDT_RST] = 0x38,
        [WDT_EN] = 0x40,
+       [WDT_BARK_TIME] = 0x4C,
        [WDT_BITE_TIME] = 0x5C,
  };

  static const u32 reg_offset_data_kpss[] = {
        [WDT_RST] = 0x4,
        [WDT_EN] = 0x8,
+       [WDT_BARK_TIME] = 0x10,
        [WDT_BITE_TIME] = 0x14,
  };

@@ -62,6 +65,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd)

        writel(0, wdt_addr(wdt, WDT_EN));
        writel(1, wdt_addr(wdt, WDT_RST));
+       writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
        writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
        writel(1, wdt_addr(wdt, WDT_EN));
        return 0;
@@ -104,6 +108,7 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, 
unsigned long action,

        writel(0, wdt_addr(wdt, WDT_EN));
        writel(1, wdt_addr(wdt, WDT_RST));
+       writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
        writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
        writel(1, wdt_addr(wdt, WDT_EN));



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