On Thu, Apr 07, 2016 at 01:08:33PM +0300, Roger Quadros wrote: > OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered > interrupts if not used for memory wait state insertion. > > Support these interrupts via the gpmc IRQ domain. > > The gpmc IRQ domain interrupt map is: > > 0 - NAND_fifoevent > 1 - NAND_termcount > 2 - GPMC_WAIT0 edge > 3 - GPMC_WAIT1 edge, and so on > > Signed-off-by: Roger Quadros <[email protected]> > --- > .../bindings/memory-controllers/omap-gpmc.txt | 5 +-
Acked-by: Rob Herring <[email protected]> > drivers/memory/omap-gpmc.c | 106 > +++++++++++++++++---- > 2 files changed, 92 insertions(+), 19 deletions(-)
