On 22/04/16 06:33, Leo Li wrote:
> On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier <[email protected]> wrote:
>> On Mon, 7 Mar 2016 11:36:22 +0800
>> Minghuan Lian <[email protected]> wrote:
>>
>>> Some kind of NXP Layerscape SoC provides a MSI
>>> implementation which uses two SCFG registers MSIIR and
>>> MSIR to support 32 MSI interrupts for each PCIe controller.
>>> The patch is to support it.
>>>
>>> Signed-off-by: Minghuan Lian <[email protected]>
>>
>> Acked-by: Marc Zyngier <[email protected]>
>>
>> The DT binding still needs an Ack from the DT maintainers though (cc'd).
>
> Marc,
>
> Who will be responsible to pick this driver? I see you are also one
> of the maintainers for irqchip. Can you pick up the driver? The
> binding has already gotten ACKed by the device tree maintainer.
Can you point me to this Ack? I can't see any trace of it in my Inbox.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
