Commit-ID: 3cfe2e8bc1cf74d78df6fe5ca3a1e1805472a004 Gitweb: http://git.kernel.org/tip/3cfe2e8bc1cf74d78df6fe5ca3a1e1805472a004 Author: Will Deacon <will.dea...@arm.com> AuthorDate: Tue, 26 Apr 2016 10:22:07 -0700 Committer: Ingo Molnar <mi...@kernel.org> CommitDate: Thu, 28 Apr 2016 10:57:51 +0200
locking/Documentation: Clarify that ACQUIRE applies to loads, RELEASE applies to stores For compound atomics performing both a load and a store operation, make it clear that _acquire and _release variants refer only to the load and store portions of compound atomic. For example, xchg_acquire is an xchg operation where the load takes on ACQUIRE semantics. Signed-off-by: Will Deacon <will.dea...@arm.com> Signed-off-by: Paul E. McKenney <paul...@linux.vnet.ibm.com> Acked-by: Peter Zijlstra (Intel) <pet...@infradead.org> Cc: Linus Torvalds <torva...@linux-foundation.org> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Thomas Gleixner <t...@linutronix.de> Cc: cor...@lwn.net Cc: d...@stgolabs.net Cc: dhowe...@redhat.com Cc: linux-...@vger.kernel.org Link: http://lkml.kernel.org/r/1461691328-5429-3-git-send-email-paul...@linux.vnet.ibm.com Signed-off-by: Ingo Molnar <mi...@kernel.org> --- Documentation/memory-barriers.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 8b11e54..147ae8e 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -498,6 +498,11 @@ And a couple of implicit varieties: This means that ACQUIRE acts as a minimal "acquire" operation and RELEASE acts as a minimal "release" operation. +A subset of the atomic operations described in atomic_ops.txt have ACQUIRE +and RELEASE variants in addition to fully-ordered and relaxed (no barrier +semantics) definitions. For compound atomics performing both a load and a +store, ACQUIRE semantics apply only to the load and RELEASE semantics apply +only to the store portion of the operation. Memory barriers are only required where there's a possibility of interaction between two CPUs or between a CPU and a device. If it can be guaranteed that
