4.5-stable review patch. If anyone has any objections, please let me know.
------------------ From: David Rivshin <[email protected]> commit 7b0883f33809ff0aeca9848193c31629a752bb77 upstream. When converting period and duty_cycle from nanoseconds to fclk cycles, the error introduced by the integer division can be appreciable, especially in the case of slow fclk or short period. Use DIV_ROUND_CLOSEST_ULL() so that the error is kept to +/- 0.5 clock cycles. Fixes: 6604c6556db9 ("pwm: Add PWM driver for OMAP using dual-mode timers") Signed-off-by: David Rivshin <[email protected]> Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]> --- drivers/pwm/pwm-omap-dmtimer.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) --- a/drivers/pwm/pwm-omap-dmtimer.c +++ b/drivers/pwm/pwm-omap-dmtimer.c @@ -49,11 +49,7 @@ to_pwm_omap_dmtimer_chip(struct pwm_chip static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns) { - u64 c = (u64)clk_rate * ns; - - do_div(c, NSEC_PER_SEC); - - return c; + return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC); } static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
