Hi Paul,
On 18/05/16 23:34, Paul Burton wrote:
On Wed, May 18, 2016 at 05:12:36PM +0100, Matt Redfearn wrote:
When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VPE to ensure
that all VPEs in the core have a consistent virtual memory map.
The EVA configuration of secondary cores is dealt with when starting the
core via the CM.
Signed-off-by: Matt Redfearn <matt.redfe...@imgtec.com>
---
Changes in v2:
- Skip check for config3 existing - we know it must to be doing
multithreading
- Use a unique lable name in the function
arch/mips/kernel/cps-vec.S | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index ac81edd44563..f8eae9189e38 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -431,6 +431,21 @@ LEAF(mips_cps_boot_vpes)
mfc0 t0, CP0_CONFIG
mttc0 t0, CP0_CONFIG
+ /*
+ * Copy the EVA config from this VPE if the CPU supports it.
+ * CONFIG3 must exist to be running MT startup - just read it.
+ */
+ mfc0 t0, CP0_CONFIG, 3
+ and t0, t0, MIPS_CONF3_SC
Tiny nit - I'd prefer "andi" here since we're using an immediate. The
assembler will figure it out though, so it's not a big deal.
Yeah, I would have too, and I did have that to start off with, but the
assembler gave me:
arch/mips/kernel/cps-vec.S: Assembler messages:
arch/mips/kernel/cps-vec.S:450: Error: operand 3 out of range `andi
$8,$8,((1)<<25)'
So I fell back to letting the assembler generate the LUI and AND.
For both in the series:
Reviewed-by: Paul Burton <paul.bur...@imgtec.com>
Thanks Paul,
Matt
Thanks,
Paul
+ beqz t0, 3f
+ nop
+ mfc0 t0, CP0_SEGCTL0
+ mttc0 t0, CP0_SEGCTL0
+ mfc0 t0, CP0_SEGCTL1
+ mttc0 t0, CP0_SEGCTL1
+ mfc0 t0, CP0_SEGCTL2
+ mttc0 t0, CP0_SEGCTL2
+3:
/* Ensure no software interrupts are pending */
mttc0 zero, CP0_CAUSE
mttc0 zero, CP0_STATUS
--
2.5.0
