(resending to MLs for the record -- previous message bounced) El viernes, 10 de junio de 2016, Alexandre Belloni <[email protected]> escribió: > > Hi, > > On 13/05/2016 at 13:09:37 +0200, Guillermo Rodriguez wrote : > > When disabling a PWM channel, the PWM clock was being stopped > > immediately after writing to PWM_DIS. As a result, the disabling > > of the PWM channel did not complete properly, and the PWM output > > might be left at the wrong level. > > > > Fix this by waiting for the channel to be effectively disabled > > (by checking the PWM_SR register) before disabling the clock. > > > > Signed-off-by: Guillermo Rodriguez <[email protected]> > > --- > > drivers/pwm/pwm-atmel.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c > > index 0e4bd4e..a714434 100644 > > --- a/drivers/pwm/pwm-atmel.c > > +++ b/drivers/pwm/pwm-atmel.c > > @@ -271,6 +271,16 @@ static void atmel_pwm_disable(struct pwm_chip *chip, > > struct pwm_device *pwm) > > mutex_unlock(&atmel_pwm->isr_lock); > > atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); > > > > + /* > > + * Wait for the PWM channel disable operation to be effective before > > + * stopping the clock. > > + */ > > + timeout = jiffies + 2 * HZ; > > + while ((atmel_pwm_readl(atmel_pwm, PWM_SR)& (1 << pwm->hwpwm)) && > > + time_before(jiffies, timeout)) { > > + usleep_range(10, 100); > > + } > > + > > While this seems good, can you tell on which SoC you observed that? I'd > like to understand whether this is only on v1 or v2 or both.
I observed it on a sama5d3, however this article from atmel's KB would seem to suggest that it is not specific to this SoC: http://atmel.force.com/support/pkb_mobile#/articles/en_US/FAQ/Why-PWM-Channel-Polarity-Inversion Guillermo
