On 06/08, Roman Volkov wrote: > From: Roman Volkov <[email protected]> > > PLL clock on WM8650 is calculated in the following way: > > M * parent [O1] => / P [O2] => / D [O3] > > Where O2 is 600MHz >= (M * parent) / P >= 300MHz. > > Current algorithm does not met this requirement, so that the > function may return rates which are not supported by the hardware. > > This patch fixes the algorithm and simplifies the code, reducing > the calculation time by ~10000 times (according to usermode app) by > removing the nested loops. > > Signed-off-by: Roman Volkov <[email protected]> > ---
Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
