On Sat, Jul 30, 2016 at 04:27:15PM +0200, codekip...@gmail.com wrote: > From: Marcus Cooper <codekip...@gmail.com> > > The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its > reset is controlled via a separate reset controller. > > Signed-off-by: Marcus Cooper <codekip...@gmail.com> > --- > Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt > b/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt > index 13503aa..4fe80f7 100644 > --- a/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt > +++ b/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt > @@ -9,6 +9,7 @@ Required properties: > > - compatible : should be one of the following: > - "allwinner,sun4i-a10-spdif": for the Allwinner A10 SoC > + - "allwinner,sun6i-a31-spdif": for the Allwinner A31 SoC > > - reg : Offset and length of the register set for the > device. > > @@ -25,6 +26,8 @@ Required properties: > "apb" clock for the spdif bus. > "spdif" clock for spdif controller. > > + - reset : reset specifier for the ahb reset (A31 and newer only)
Isn't it resets ? (plural) Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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