On 15/06/16 16:36, Vladimir Murzin wrote: > On 13/06/16 15:12, Alexandre TORGUE wrote: >> According to ARM AN321 (section 4.12): >> >> "If the vector table is in writable memory such as SRAM, either relocated >> by VTOR or a device dependent memory remapping mechanism, then >> architecturally a memory barrier instruction is required after the vector >> table entry is updated, and if the exception is to be activated >> immediately" >> >> Signed-off-by: Maxime Coquelin <[email protected]> >> Signed-off-by: Alexandre TORGUE <[email protected]> >> > > Reviewed-by: Vladimir Murzin <[email protected]> > >> diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S >> index 7229d8d..2ddc435 100644 >> --- a/arch/arm/mm/proc-v7m.S >> +++ b/arch/arm/mm/proc-v7m.S >> @@ -104,6 +104,7 @@ __v7m_setup: >> badr r1, 1f >> ldr r5, [r12, #11 * 4] @ read the SVC vector entry >> str r1, [r12, #11 * 4] @ write the temporary SVC vector entry >> + dsb >> mov r6, lr @ save LR >> ldr sp, =init_thread_union + THREAD_START_SP >> cpsie i >> >
Alex, xan you drop it into RMK's Patch system [1] please? [1] http://www.armlinux.org.uk/developer/patches/ Thanks Vladimir > > _______________________________________________ > linux-arm-kernel mailing list > [email protected] > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > >
