On Mon, Aug 08, 2016 at 06:21:45PM +0100, Andre Przywara wrote: > The Allwinner H3 SoC introduced bus clock gates with potentially > different parents per clock gate register. The H3 driver chose to > hardcode the actual parent clock relation in the code. > Add a new driver (which has the potential to drive the H3 and also > the simple clock gates as well) which uses the power of DT to describe > this relationship in an elegant and flexible way. > Using one subnode for every parent clock we get away with a single > DT compatible match, which can be used as a fallback value in the > actual DTs without the need to add specific compatible strings to the > code. This avoids adding a new driver or function for every new SoC. > > Signed-off-by: Andre Przywara <[email protected]> > Acked-by: Jean-Francois Moine <[email protected]> > --- > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk-multi-gates.c | 105 > ++++++++++++++++++++++++++++++++++++
Aside from my initial objections (that I still have), drivers/clk/sunxi is in maintainance-only mode, we won't merge any new drivers there. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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