On Fri, 26 Aug 2016, Thomas Gleixner wrote:
> On Thu, 25 Aug 2016, Bin Gao wrote:
> > On Wed, Aug 24, 2016 at 10:51:20AM +0200, Thomas Gleixner wrote:
> > > On Tue, 16 Aug 2016, Bin Gao wrote:
> > > > On some newer Intel x86 processors/SoCs the TSC frequency can be
> > > > directly
> > > > calculated by factors read from specific MSR registers or from a cpuid
> > > > leaf (0x15). TSC frequency calculated by native msr/cpuid is absolutely
> > > > accurate so we should always skip calibrating TSC aginst another clock,
> > > > e.g. PIT, HPET, etc. So we want to skip the refined calibration by
> > > > setting
> > > > the X86_FEATURE_TSC_RELIABLE flag. Existing code setting the flag by
> > > > set_cpu_cap() doesn't work as the flag is cleared later in
> > > > identify_cpu().
> > > > A cpu caps flag is not cleared only if it's set by
> > > > setup_force_cpu_cap().
> > > > This patch converted set_cpu_cap() to setup_force_cpu_cap() to ensure
> > > > refined calibration is skipped.
> > > >
> > > > We had a test on Intel CherryTrail platform: the 24 hours time drift is
> > > > 3.6 seconds if refined calibration was not skipped while the drift is
> > > > less
> > > > than 0.6 second when refined calibration was skipped.
> > > >
> > > > Correctly setting the X86_FEATURE_TSC_RELIABLE flag also guarantees TSC
> > > > is
> > > > not monitored by timekeeping watchdog because on most of these system
> > > > TSC
> > > > is the only reliable clocksource. HPET, for instance, works but may not
> > > > be reliable. So kernel may report a physically reliable TSC is not
> > > > reliable
> > > > just because a physically not reliable HPET is acting as timekeeping
> > > > watchdog.
> > >
> > > What about non SoC systems where the MSR is available, but we still see
> > > that
> > > cross socket TSC wreckage? This change will prevent the watchdog from
> > > detecting that.
> >
> > MSR is only available on Intel Atom SoCs. There is no such a multi-socket
> > system.
>
> Fair enough.
Second thoughts. We should seperate the calibration aspect from the reliablity
aspect.
If a MSR/CPUID readout provides reliable calibration then this does not tell
us about the reliablity (i.e. no watchdog required). So having two flags for
this - and sure you can set both on those SoCs is the proper solution.
Thanks,
tglx
