On 08/29/2016 02:27 PM, gabriel.fernan...@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernan...@st.com>
> 
> It is necessary to properly configure these clocks in order
> to address 720p and 1080p HDMI resolution.
> 
> Signed-off-by: Vincent Abriou <vincent.abr...@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernan...@st.com>
> Acked-by: Peter Griffin <peter.grif...@linaro.org>
> ---
>  arch/arm/boot/dts/stih407.dtsi | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
> index d60f0d8..291ffac 100644
> --- a/arch/arm/boot/dts/stih407.dtsi
> +++ b/arch/arm/boot/dts/stih407.dtsi
> @@ -16,7 +16,10 @@
>                       #size-cells = <1>;
>  
>                       assigned-clocks = <&clk_s_d2_quadfs 0>,
> -                                       <&clk_s_d2_quadfs 0>,
> +                                       <&clk_s_d2_quadfs 1>,
> +                                       <&clk_s_c0_pll1 0>,
> +                                       <&clk_s_c0_flexgen CLK_COMPO_DVP>,
> +                                       <&clk_s_c0_flexgen CLK_MAIN_DISP>,
>                                         <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
>                                         <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
>                                         <&clk_s_d2_flexgen CLK_PIX_GDP1>,
> @@ -26,14 +29,21 @@
>  
>                       assigned-clock-parents = <0>,
>                                                <0>,
> +                                              <0>,
> +                                              <&clk_s_c0_pll1 0>,
> +                                              <&clk_s_c0_pll1 0>,
>                                                <&clk_s_d2_quadfs 0>,
> -                                              <&clk_s_d2_quadfs 0>,
> +                                              <&clk_s_d2_quadfs 1>,
>                                                <&clk_s_d2_quadfs 0>,
>                                                <&clk_s_d2_quadfs 0>,
>                                                <&clk_s_d2_quadfs 0>,
>                                                <&clk_s_d2_quadfs 0>;
>  
> -                     assigned-clock-rates = <297000000>, <297000000>;
> +                     assigned-clock-rates = <297000000>,
> +                                            <108000000>,
> +                                            <0>,
> +                                            <400000000>,
> +                                            <400000000>;
>  
>                       ranges;
>  
> 
Hi Gabriel

Applied on STi tree for v4.9

Thanks

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