If the FTM counter reaches the FTM_MOD value between the reading of the
TOF bit and the writing of 0 to the TOF bit, the process of clearing the
TOF bit does not work as expected when FTMx_CONF[NUMTOF] != 0 and the
current TOF count is less than FTMx_CONF[NUMTOF]. If the above condition
is met, the TOF bit remains set. If the TOF interrupt is enabled
(FTMx_SC[TOIE] = 1), the TOF interrupt also remains asserted.

Above is the errata discription

The workaround is clearing TOF bit until it is cleaned(FTM counter doesn't
always reache the FTM_MOD anyway),which may cost some cycles.

Signed-off-by: Meng Yi <meng...@nxp.com>
Change in V2:
-add timeout into IRQ context(suggested by Alexander)
 drivers/clocksource/fsl_ftm_timer.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/fsl_ftm_timer.c 
index 738515b..86f9186 100644
--- a/drivers/clocksource/fsl_ftm_timer.c
+++ b/drivers/clocksource/fsl_ftm_timer.c
@@ -83,11 +83,13 @@ static inline void ftm_counter_disable(void __iomem *base)
 static inline void ftm_irq_acknowledge(void __iomem *base)
-       u32 val;
+       unsigned long timeout = jiffies + msecs_to_jiffies(100);
-       val = ftm_readl(base + FTM_SC);
-       val &= ~FTM_SC_TOF;
-       ftm_writel(val, base + FTM_SC);
+       /*read and clean the FTM_SC_TOF bit until its cleared*/
+       while ((FTM_SC_TOF & ftm_readl(base + FTM_SC)) &&
+               time_before(jiffies, timeout))
+               ftm_writel(ftm_readl(base + FTM_SC) & (~FTM_SC_TOF),
+                          base + FTM_SC);
 static inline void ftm_irq_enable(void __iomem *base)

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