Hi,

On Wed, Oct 12, 2016 at 12:20 PM, Icenowy Zheng <icen...@aosc.xyz> wrote:
> The PWM controller in A31 is different with other Allwinner SoCs, with a
> control register per channel (in other SoCs the control register is
> shared), and each channel are allocated 16 bytes of address (but only 8
> bytes are used.). The register map in one channel is just like a
> single-channel A10 PWM controller, however, A31 have a different
> prescaler table than other SoCs.
>
> In order to use the driver for all 4 channels, device nodes should be
> created per channel.

I think Maxime wants you to support the different register offsets
in this driver, and have all 4 channels in the same device (node).

ChenYu


> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
> ---
>  drivers/pwm/pwm-sun4i.c | 37 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index 03a99a5..3e93bdf 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -46,7 +46,7 @@
>
>  #define BIT_CH(bit, chan)      ((bit) << ((chan) * PWMCH_OFFSET))
>
> -static const u32 prescaler_table[] = {
> +static const u32 prescaler_table_a10[] = {
>         120,
>         180,
>         240,
> @@ -65,10 +65,30 @@ static const u32 prescaler_table[] = {
>         0, /* Actually 1 but tested separately */
>  };
>
> +static const u32 prescaler_table_a31[] = {
> +       1,
> +       2,
> +       4,
> +       8,
> +       16,
> +       32,
> +       64,
> +       0,
> +       0,
> +       0,
> +       0,
> +       0,
> +       0,
> +       0,
> +       0,
> +       0,
> +};
> +
>  struct sun4i_pwm_data {
>         bool has_prescaler_bypass;
>         bool has_rdy;
>         unsigned int npwm;
> +       const u32 *prescaler_table;
>  };
>
>  struct sun4i_pwm_chip {
> @@ -100,6 +120,7 @@ static int sun4i_pwm_config(struct pwm_chip *chip, struct 
> pwm_device *pwm,
>                             int duty_ns, int period_ns)
>  {
>         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
> +       const u32 *prescaler_table = sun4i_pwm->data->prescaler_table;
>         u32 prd, dty, val, clk_gate;
>         u64 clk_rate, div = 0;
>         unsigned int prescaler = 0;
> @@ -264,24 +285,35 @@ static const struct sun4i_pwm_data sun4i_pwm_data_a10 = 
> {
>         .has_prescaler_bypass = false,
>         .has_rdy = false,
>         .npwm = 2,
> +       .prescaler_table = prescaler_table_a10,
>  };
>
>  static const struct sun4i_pwm_data sun4i_pwm_data_a10s = {
>         .has_prescaler_bypass = true,
>         .has_rdy = true,
>         .npwm = 2,
> +       .prescaler_table = prescaler_table_a10,
>  };
>
>  static const struct sun4i_pwm_data sun4i_pwm_data_a13 = {
>         .has_prescaler_bypass = true,
>         .has_rdy = true,
>         .npwm = 1,
> +       .prescaler_table = prescaler_table_a10,
>  };
>
>  static const struct sun4i_pwm_data sun4i_pwm_data_a20 = {
>         .has_prescaler_bypass = true,
>         .has_rdy = true,
>         .npwm = 2,
> +       .prescaler_table = prescaler_table_a10,
> +};
> +
> +static const struct sun4i_pwm_data sun4i_pwm_data_a31 = {
> +       .has_prescaler_bypass = false,
> +       .has_rdy = true,
> +       .npwm = 1,
> +       .prescaler_table = prescaler_table_a31,
>  };
>
>  static const struct of_device_id sun4i_pwm_dt_ids[] = {
> @@ -298,6 +330,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
>                 .compatible = "allwinner,sun7i-a20-pwm",
>                 .data = &sun4i_pwm_data_a20,
>         }, {
> +               .compatible = "allwinner,sun6i-a31-pwm",
> +               .data = &sun4i_pwm_data_a31
> +       }, {
>                 /* sentinel */
>         },
>  };
> --
> 2.10.1
>
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