From: Wanpeng Li <wanpeng...@hotmail.com>

Check apic_lvtt_tscdeadline() mode directly instead of apic_lvtt_oneshot()
and apic_lvtt_period() to guarantee the timer is in tsc-deadline mode when
rdmsr MSR_IA32_TSCDEADLINE.

Suggsted-by: Radim Krčmář <rkrc...@redhat.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Radim Krčmář <rkrc...@redhat.com>
Cc: Yunhong Jiang <yunhong.ji...@intel.com>
Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com>
---
 arch/x86/kvm/lapic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index dad743e..dce6c0b 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1711,8 +1711,8 @@ u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
 {
        struct kvm_lapic *apic = vcpu->arch.apic;
 
-       if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
-                       apic_lvtt_period(apic))
+       if (!lapic_in_kernel(vcpu) ||
+               !apic_lvtt_tscdeadline(apic))
                return 0;
 
        return apic->lapic_timer.tscdeadline;
-- 
1.9.1

Reply via email to