From: Thomas Huth <>

3.12-stable review patch.  If anyone has any objections, please let me know.


commit fa73c3b25bd8d0d393dc6109a1dba3c2aef0451e upstream.

The MMCR2 register is available twice, one time with number 785
(privileged access), and one time with number 769 (unprivileged,
but it can be disabled completely). In former times, the Linux
kernel was using the unprivileged register 769 only, but since
commit 8dd75ccb571f3c92c ("powerpc: Use privileged SPR number
for MMCR2"), it uses the privileged register 785 instead.
The KVM-PR code then of course also switched to use the SPR 785,
but this is causing older guest kernels to crash, since these
kernels still access 769 instead. So to support older kernels
with KVM-PR again, we have to support register 769 in KVM-PR, too.

Fixes: 8dd75ccb571f3c92c48014b3dabd3d51a115ab41
Signed-off-by: Thomas Huth <>
Signed-off-by: Paul Mackerras <>
Signed-off-by: Jiri Slaby <>
 arch/powerpc/include/asm/reg.h    | 1 +
 arch/powerpc/kvm/book3s_emulate.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 53762dbf547c..3c612f658988 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -648,6 +648,7 @@
 #define   MMCR0_FCHV   0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1     798
 #define SPRN_MMCR2     785
+#define SPRN_UMMCR2    769
 #define SPRN_MMCRA     0x312
 #define   MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
diff --git a/arch/powerpc/kvm/book3s_emulate.c 
index cda2cba56915..5d509ee39465 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -465,6 +465,7 @@ int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int 
sprn, ulong spr_val)
        case SPRN_MMCR0:
        case SPRN_MMCR1:
        case SPRN_MMCR2:
+       case SPRN_UMMCR2:
@@ -570,6 +571,7 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int 
sprn, ulong *spr_val)
        case SPRN_MMCR0:
        case SPRN_MMCR1:
        case SPRN_MMCR2:
+       case SPRN_UMMCR2:
        case SPRN_TIR:
                *spr_val = 0;

Reply via email to