4.8-stable review patch. If anyone has any objections, please let me know.
------------------ From: Bjorn Helgaas <[email protected]> commit 8dd99bca7bfa4b62753b556c45d26f45ec9da6e6 upstream. The tegra_pcie_phy_disable() path called pads_writel() with arguments in the wrong order. Swap them to be the "value, offset" order expected by pads_writel(). Fixes: 6fe7c187e026 ("PCI: tegra: Support per-lane PHYs") Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Thierry Reding <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]> --- drivers/pci/host/pci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -856,7 +856,7 @@ static int tegra_pcie_phy_disable(struct /* override IDDQ */ value = pads_readl(pcie, PADS_CTL); value |= PADS_CTL_IDDQ_1L; - pads_writel(pcie, PADS_CTL, value); + pads_writel(pcie, value, PADS_CTL); /* reset PLL */ value = pads_readl(pcie, soc->pads_pll_ctl);
