From: Tony Luck <[email protected]> Intel Xeons from Ivy Bridge onwards support a processor identification number. Kernels v4.9 and higher include it in the "mce" record.
Signed-off-by: Tony Luck <[email protected]> --- mcelog.c | 3 +++ mcelog.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/mcelog.c b/mcelog.c index 7214a0d23f65..e79996db9b5b 100644 --- a/mcelog.c +++ b/mcelog.c @@ -441,6 +441,9 @@ static void dump_mce(struct mce *m, unsigned recordlen) if (n > 0) Wprintf("\n"); + if (recordlen >= offsetof(struct mce, ppin) && m->ppin) + n += Wprintf("PPIN %llx\n", m->ppin); + if (recordlen >= offsetof(struct mce, cpuid) && m->cpuid) { u32 fam, mod; parse_cpuid(m->cpuid, &fam, &mod); diff --git a/mcelog.h b/mcelog.h index 254b3a092fba..9a54077e5474 100644 --- a/mcelog.h +++ b/mcelog.h @@ -31,6 +31,9 @@ struct mce { __u32 socketid; /* CPU socket ID */ __u32 apicid; /* CPU initial apic ID */ __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ + __u64 synd; /* MCA_SYND MSR: only valid on SMCA systems */ + __u64 ipid; /* MCA_IPID MSR: only valid on SMCA systems */ + __u64 ppin; /* Protected Processor Inventory Number */ }; #define X86_VENDOR_INTEL 0 -- 2.7.4
