On Tue, 15 Nov 2016, Andy Shevchenko wrote: > Enable MWI mechanism if PCI bus master supports it. > > It might be potential benefit in some cases. Documentation [1] says that > standard Memory Write might supply more current data than in the CPU modified > cache line and "trashing a line in the cache may trash some data that is more > current that in the memory line". This allows to avoid potential retries and > other performance degradation issues on the bus. > > [1] PCI System Architecture, 4th edition, ISBN: 0-201-30974-2, pp.117-119. > > Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com> > --- > In v2: > - extend commit message > drivers/mfd/intel-lpss-pci.c | 1 + > 1 file changed, 1 insertion(+)
Applied, thanks. > diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c > index 50e78db..4756153 100644 > --- a/drivers/mfd/intel-lpss-pci.c > +++ b/drivers/mfd/intel-lpss-pci.c > @@ -41,6 +41,7 @@ static int intel_lpss_pci_probe(struct pci_dev *pdev, > > /* Probably it is enough to set this for iDMA capable devices only */ > pci_set_master(pdev); > + pci_try_set_mwi(pdev); > > ret = intel_lpss_probe(&pdev->dev, info); > if (ret) -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
