On Tue, Dec 6, 2016 at 3:53 AM, Andrew Jeffery <[email protected]> wrote:
> The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends > on bits in both the System Control Unit and the LPC Host Controller. > > The Aspeed LPC Host Controller is described as a child node of the > LPC host-range syscon device for arbitration of access by the host > controller and pinmux drivers. > > Signed-off-by: Andrew Jeffery <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Yours, Linus Walleij
