On 11/11, Christophe JAILLET wrote: > It is likely that instead of '1>64', 'q>64' was expected. > > Moreover, according to datasheet, > http://www.ti.com/lit/ds/symlink/cdce925.pdf > SCAS847I - JULY 2007 - REVISED OCTOBER 2016 > PLL settings limits are: 16 <= q <= 63 > So change the upper limit check from 64 to 63. > > Signed-off-by: Christophe JAILLET <[email protected]> > ---
Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
