On 13/01/17 09:06, Tan Xiaojun wrote: > On 2017/1/13 2:29, Sudeep Holla wrote: >> The cache hierarchy can be identified through Cache Level ID(CLIDR) >> architected system register. However in some cases it will provide >> only the number of cache levels that are integrated into the processor >> itself. In other words, it can't provide any information about the >> caches that are external and/or transparent. >> >> Some platforms require to export the information about all such external >> caches to the userspace applications via the sysfs interface. >> >> This patch adds support to override the cache levels using device tree >> to take such external non-architected caches into account. >> >> Cc: Catalin Marinas <catalin.mari...@arm.com> >> Cc: Will Deacon <will.dea...@arm.com> >> Cc: Mark Rutland <mark.rutl...@arm.com> >> Signed-off-by: Sudeep Holla <sudeep.ho...@arm.com> > > Tested-by: Tan Xiaojun <tanxiao...@huawei.com> >
Thanks for testing. -- Regards, Sudeep
