On Mon, Jan 16, 2017 at 05:56:58PM +0100, Maxime Ripard wrote: > From: Andre Przywara <[email protected]> > > The A64 has 3 MMC controllers, one of them being especially targeted to > eMMC. Among other things, it has a data strobe signal and a 8 bits data > width. > > The two other are more usual controllers that will have a 4 bits width at > most and no data strobe signal, which limits it to more usual SD or MMC > peripherals. > > Signed-off-by: Andre Przywara <[email protected]> > Signed-off-by: Maxime Ripard <[email protected]> > --- > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 39 ++++++++++++++++++++- > 1 file changed, 39 insertions(+), 0 deletions(-) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > index 99b6bb1e141c..143e9706438f 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -299,6 +299,45 @@ > #size-cells = <0>; > }; > > + mmc0: mmc@1c0f000 { > + compatible = "allwinner,sun50i-a64-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC0>; > + reset-names = "ahb"; > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc1: mmc@1c10000 { > + compatible = "allwinner,sun50i-a64-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC1>; > + reset-names = "ahb"; > + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc2: mmc@1c11000 { > + compatible = "allwinner,sun50i-a64-emmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC2>; > + reset-names = "ahb"; > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > gic: interrupt-controller@1c81000 { > compatible = "arm,gic-400"; > reg = <0x01c81000 0x1000>,
Hello It seems that mmc node is after i2c@1c2b400 so not in address order. Regards Corentin Labbe
