On 10/01/17 09:00, Ritesh Harjani wrote: > From: Subhash Jadavani <subha...@codeaurora.org> > > Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay. > We may see data CRC errors if it's programmed for any other delay > value. > > Signed-off-by: Subhash Jadavani <subha...@codeaurora.org> > Signed-off-by: Ritesh Harjani <rite...@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hun...@intel.com> > --- > drivers/mmc/host/sdhci-msm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index a028568..84d29dd 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -679,7 +679,7 @@ static int sdhci_msm_cdclp533_calibration(struct > sdhci_host *host) > writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); > writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); > writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); > - writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); > + writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); > writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); > writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); > >
