This erratum describes the limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions and on those platforms the MSI transactions has to be bypassed by SMMU. The IIDR register of the GICv3 ITS on these platforms are not properly populated to differentiate the hardware, hence describe it in device tree.
Signed-off-by: shameer <[email protected]> --- .../devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cda..84af301 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,12 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optional +- hisilicon,erratum-161010801 : A boolean property. Indicates the presence of + erratum 161010801, which says that these platforms doesn't support SMMU + mapping for MSI transactions and those transactions has to be bypassed + by SMMU. + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. -- 1.9.1
