On 21/02/17 12:57, Robin Murphy wrote: > On 15/02/17 09:59, Vladimir Murzin wrote: >> Now, we have dedicated non-cacheable region for consistent DMA >> operations. However, that region can still be marked as bufferable by >> MPU, so it'd be safer to have barriers by default. > > Makes sense - plenty of cases want their DMA buffers to still be > write-combining (e.g. framebuffers have already been mentioned here), > for which strongly-ordered mappings won't do. Plus you don't exactly > have a choice if you've no MPU and have fixed Normal attributes for your > RAM region. > > Reviewed-by: Robin Murphy <[email protected]>
Thanks! Vladimir > >> Tested-by: Benjamin Gaignard <[email protected]> >> Tested-by: Andras Szemzo <[email protected]> >> Tested-by: Alexandre TORGUE <[email protected]> >> Signed-off-by: Vladimir Murzin <[email protected]> >> --- >> arch/arm/mm/Kconfig | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig >> index 0b79f12..64a1465c 100644 >> --- a/arch/arm/mm/Kconfig >> +++ b/arch/arm/mm/Kconfig >> @@ -1029,7 +1029,7 @@ config ARM_L1_CACHE_SHIFT >> >> config ARM_DMA_MEM_BUFFERABLE >> bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && >> !CPU_V7 >> - default y if CPU_V6 || CPU_V6K || CPU_V7 >> + default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M >> help >> Historically, the kernel has used strongly ordered mappings to >> provide DMA coherent memory. With the advent of ARMv7, mapping >> > >
