Am Dienstag, den 21.03.2017, 06:42 -0700 schrieb Andrey Smirnov: > Save a bit of time and avoid going through link speed change procedure > in configuration where link max speed is limited to Gen1 in DT. > > Cc: [email protected] > Cc: Lucas Stach <[email protected]> > Cc: Bjorn Helgaas <[email protected]> > Cc: Fabio Estevam <[email protected]> > Cc: Dong Aisheng <[email protected]> > Cc: [email protected] > Cc: [email protected] > Signed-off-by: Andrey Smirnov <[email protected]>
Reviewed-by: Lucas Stach <[email protected]> > --- > drivers/pci/dwc/pci-imx6.c | 52 > +++++++++++++++++++++++----------------------- > 1 file changed, 26 insertions(+), 26 deletions(-) > > diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c > index c731e41..9407c03 100644 > --- a/drivers/pci/dwc/pci-imx6.c > +++ b/drivers/pci/dwc/pci-imx6.c > @@ -533,40 +533,40 @@ static int imx6_pcie_establish_link(struct imx6_pcie > *imx6_pcie) > tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; > tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; > dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); > - } else { > - dev_info(dev, "Link: Gen2 disabled\n"); > - } > - > - /* > - * Start Directed Speed Change so the best possible speed both link > - * partners support can be negotiated. > - */ > - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > - tmp |= PORT_LOGIC_SPEED_CHANGE; > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); > > - if (imx6_pcie->variant != IMX7D) { > /* > - * On i.MX7, DIRECT_SPEED_CHANGE behaves differently > - * from i.MX6 family when no link speed transition > - * occurs and we go Gen1 -> yep, Gen1. The difference > - * is that, in such case, it will not be cleared by HW > - * which will cause the following code to report false > - * failure. > + * Start Directed Speed Change so the best possible > + * speed both link partners support can be negotiated. > */ > + tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > + tmp |= PORT_LOGIC_SPEED_CHANGE; > + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); > + > + if (imx6_pcie->variant != IMX7D) { > + /* > + * On i.MX7, DIRECT_SPEED_CHANGE behaves differently > + * from i.MX6 family when no link speed transition > + * occurs and we go Gen1 -> yep, Gen1. The difference > + * is that, in such case, it will not be cleared by HW > + * which will cause the following code to report false > + * failure. > + */ > + > + ret = imx6_pcie_wait_for_speed_change(imx6_pcie); > + if (ret) { > + dev_err(dev, "Failed to bring link up!\n"); > + goto err_reset_phy; > + } > + } > > - ret = imx6_pcie_wait_for_speed_change(imx6_pcie); > + /* Make sure link training is finished as well! */ > + ret = imx6_pcie_wait_for_link(imx6_pcie); > if (ret) { > dev_err(dev, "Failed to bring link up!\n"); > goto err_reset_phy; > } > - } > - > - /* Make sure link training is finished as well! */ > - ret = imx6_pcie_wait_for_link(imx6_pcie); > - if (ret) { > - dev_err(dev, "Failed to bring link up!\n"); > - goto err_reset_phy; > + } else { > + dev_info(dev, "Link: Gen2 disabled\n"); > } > > tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
