PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieral...@arm.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Cc: Bjorn Helgaas <bhelg...@google.com>
Cc: Zhou Wang <wangzh...@hisilicon.com>
---
 drivers/pci/dwc/pcie-hisi.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
index fd66a31..66a91b2 100644
--- a/drivers/pci/dwc/pcie-hisi.c
+++ b/drivers/pci/dwc/pcie-hisi.c
@@ -99,7 +99,7 @@ static int hisi_pcie_init(struct pci_config_window *cfg)
                return -ENOMEM;
        }
 
-       reg_base = devm_ioremap(dev, res->start, resource_size(res));
+       reg_base = devm_ioremap_nopost(dev, res->start, resource_size(res));
        if (!reg_base)
                return -ENOMEM;
 
@@ -296,10 +296,9 @@ static int hisi_pcie_probe(struct platform_device *pdev)
        }
 
        reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
-       pci->dbi_base = devm_ioremap_resource(dev, reg);
+       pci->dbi_base = devm_ioremap_nopost_resource(dev, reg);
        if (IS_ERR(pci->dbi_base))
                return PTR_ERR(pci->dbi_base);
-
        platform_set_drvdata(pdev, hisi_pcie);
 
        ret = hisi_add_pcie_port(hisi_pcie, pdev);
@@ -360,7 +359,7 @@ static int hisi_pcie_platform_init(struct pci_config_window 
*cfg)
                return -EINVAL;
        }
 
-       reg_base = devm_ioremap(dev, res->start, resource_size(res));
+       reg_base = devm_ioremap_nopost(dev, res->start, resource_size(res));
        if (!reg_base)
                return -ENOMEM;
 
-- 
2.10.0

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