> On 31/03/17 , Marc Zyngier wrote: > On 31/03/17 09:01, Thomas Gleixner wrote: > > On Thu, 30 Mar 2017, Aniruddha Banerjee wrote: > > > >> add IRQF_TRIGGER_MASK on PPI by default so that the PPIs are not > >> configured as edge-triggered, which may be wrong for certain GIC > >> implementations such as the GIC-400 > > > > The above is just useless blurb. > > > > I can't figure out at all WHY a generic interface has anything to do > > with edge trigger configuration. > > > > I assume this is (Nvidia) GIC specific nonsense, so why are you > > inflicting this on every caller of this interface unconditionally w/o > > explaining what the impact of this change might be and why it does not > > cause havoc for any existing caller? > > > > This is function is implemented in kernel/irq/ not in foo/gic/ so you > > better come up with some coherent explanation. > > Indeed. I'm not aware of anything wrong so far with GIC400, so this is most > likely > referring to an integration issue. > > Furthermore, PPI triggers are usually not configurable on GIC400. My bet is > that this is > only a DT issue, but in the absence of any coherent justification, it is hard > to make an > educated guess...
That was an awesome guess and we were in fact doing something very wrong in the DT. In the GIC-400 implementation, the PPI triggers are read-only. I was trying to configure the PPI as edge-triggered, and the writes were dropped in the process. A big thank you to Jon Hunter and Marc for pointing this out. Regards, Aniruddha.
