On Thu, 30 Mar 2017 18:26:01 +0100 Simon Hatliff <[email protected]> wrote:
> Hi Boris, Linus, > > On 30/03/17 12:29, Boris Brezillon wrote: > > Hi Linus, > > > > On Thu, 30 Mar 2017 11:03:45 +0200 > > Linus Walleij <[email protected]> wrote: > > > >> On Wed, Mar 29, 2017 at 6:04 PM, Boris Brezillon > >> <[email protected]> wrote: > >> > >>> Add a driver for Cadence GPIO controller. > >> IIUC Cadence do a lot of things. Are there variants of this controller? > > I'll let Simon answer that one. > This is a controller that has been around since 2000. It is not > configurable in any way, so there are no variants. Cadence do not offer > any other GPIO controllers as IP. > >>> +static irqreturn_t cdns_gpio_irq_handler(int irq, void *dev) > >>> +{ > >>> + struct cdns_gpio_chip *cgpio = dev; > >>> + unsigned long status; > >>> + int hwirq; > >>> + > >>> + /* > >>> + * FIXME: If we have an edge irq that is masked we might lose it > >>> + * since reading the STATUS register clears all IRQ flags. > >>> + * We could store the status of all masked IRQ in the > >>> cdns_gpio_chip > >>> + * struct but we then have no way to re-trigger the interrupt when > >>> + * it is unmasked. > >>> + */ > >> It is marked FIXME but do you think it can even be fixed? It seems > >> like a hardware flaw. :( > > Maybe not. Unless Simon comes up with a magic register to re-trigger an > > interrupt :-). > There are no plans to update the controller. Linus, what should I do here? Drop support for edge interrupts?
