> -----Original Message----- > From: [email protected] [mailto:linux-edac- > [email protected]] On Behalf Of Borislav Petkov > Sent: Tuesday, April 18, 2017 2:39 PM > To: Ghannam, Yazen <[email protected]> > Cc: Tony Luck <[email protected]>; linux-edac <linux- > [email protected]>; lkml <[email protected]> > Subject: [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on > Intel only > > mce_usable_address() does a bunch of basic sanity checks to verify whether > the address reported with the error is usable for further processing. > However, we do check MCi_STATUS[MISCV] and that is not needed on AMD as > that bit says that there's additional information about the logged error in > the > MCi_MISCj banks. > > But we don't need that to know whether the address is usable - we only need > to know whether the physical address is valid - i.e., ADDRV. > > [ On Intel the MISCV bit is needed to perform additional checks to > determine whether the reported address is a physical one, etc. ] > > Signed-off-by: Borislav Petkov <[email protected]> > Cc: "Ghannam, Yazen" <[email protected]> > --- > > Right, so I think we don't need to look at MISCV on AMD to check whether the > address is usable because ADDRV already denotes that MCi_ADDR has the > physical address. Yes? >
We definitely don't need to look at MiscV. But the value in MCA_ADDR isn't necessarily a system physical address. It can be, or it can be a normalized address in the case of UMCs, or it can a set/way for caches. So it depends on the bank type and error type. All this may just be for SMCA systems though. I need to double check. Thanks, Yazen
