Hi, While investigating why there were no L2 cache events generated for a Cortex A53-like PMU, it turned out that none of the L2 cache events were mapped.
This is also the case for ARMv8 PMUv3, which seems a little odd considering they are defined. Thanks! Florian Fainelli (2): arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 arch/arm64/kernel/perf_event.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.9.3
