On Sat, Nov 18, 2000 at 10:43:20PM -0500, John Cavan wrote:
> Bus  1, device   0, function  0:
>   VGA compatible controller: Matrox Graphics, Inc. MGA G400 AGP (rev 5).
>     IRQ 16.
>     Master Capable.  Latency=64.  Min Gnt=16.Max Lat=32.
>     Prefetchable 32 bit memory at 0xf6000000 [0xf7ffffff].
>     Non-prefetchable 32 bit memory at 0xfeafc000 [0xfeafffff].
>     Non-prefetchable 32 bit memory at 0xfe000000 [0xfe7fffff].
> 
> But agpgart sets up:
> 
> agpgart: Maximum main memory to use for agp memory: 440M
> agpgart: Detected Intel 440BX chipset
> agpgart: AGP aperture is 32M @ 0xfa000000

AGP aperture is feature of host bridge:


00:00.0 Host bridge: Intel Corporation 440BX/ZX - 82443BX/ZX Host bridge (rev 02)
        Flags: bus master, medium devsel, latency 32
        Memory at d0000000 (32-bit, prefetchable) [size=64M]
                  ^^^^^^^^                        ^^^^^^^^^^
        Capabilities: [a0] AGP version 1.0

01:00.0 VGA compatible controller: Matrox Graphics, Inc. MGA G200 AGP (rev 01) 
(prog-if 00 [VGA])
        Subsystem: Matrox Graphics, Inc. Millennium G200 AGP
        Flags: bus master, medium devsel, latency 32, IRQ 11
        Memory at d8000000 (32-bit, prefetchable) [size=16M]
        Memory at d4000000 (32-bit, non-prefetchable) [size=16K]
        Memory at d5000000 (32-bit, non-prefetchable) [size=8M]
        Expansion ROM at <unassigned> [disabled] [size=64K]
        Capabilities: [dc] Power Management version 1
        Capabilities: [f0] AGP version 1.0

So it matters what you have listed in 00:00.0 node, not on Matrox device.

> Needless to say, the two disagree and direct rendering is disabled.
> Attached is my .config for 2.4.0-test11-pre7. I've been wading through
> the code for AGP and DRM support, but nothing jumps out at me.

> (http://www.matrox.com/mga/support/drivers/latest/home.htm)

As matrox driver contains large BLOB which does all important things
(dualhead) usual practices about binary only software applies.
                                        Best regards,
                                                Petr Vandrovec
                                                [EMAIL PROTECTED]

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