On Tue, Apr 03, 2007 at 03:55:32PM +0200, Bernhard Kaindl wrote:
> PS: I attached a program which uses msr.ko (CONFIG_X86_MSR) from
> Processor type and features
> -> [M/*] /dev/cpu/*/msr - Model-specific register support
> to dump the contents of the fixed-range MTTRs to stdout.
>
> On a two-CPU system, the output format looks like this:
>
> MSR 0x250: 1e1e1e1e1e1e1e1e | 0606060606060606 |
> MSR 0x258: 1e1e1e1e1e1e1e1e | 0606060606060606 |
> MSR 0x259: 0000000000000000 | 0000000000000000 |
> MSR 0x268: 1515151515151515 | 0505050505050505 |
> MSR 0x269: 1515151515151515 | 0505050505050505 |
> MSR 0x26a: 0000000000000000 | 0000000000000000 |
> MSR 0x26b: 0000000000000000 | 0000000000000000 |
> MSR 0x26c: 1515151500000000 | 0505050500000000 |
> MSR 0x26d: 1515151515151515 | 0505050505050505 |
> MSR 0x26e: 1515151515151515 | 0505050505050505 |
> MSR 0x26f: 1515151515151515 | 0505050505050505 |
FWIW, x86info --mtrr would have done this for you :)
> To have a sane MTRR setup the MTRRs of the CPUs should always
> match, but this has so far not lead to problems, it seems. However,
> Intel and AMD manuals tell us to keep MTRRs in sync for good reasons.
Indeed. From a quick lookover, I don't see anything obviously
wrong in your patches, though Jan and Andi probably remember more
gory details about that code than I'll admit to.
Dave
--
http://www.codemonkey.org.uk
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