From: Yazen Ghannam <yazen.ghan...@amd.com>
The value of MCA_STATUS is used as the MSR when clearing MCA_STATUS.
This may cause the following warning:
unchecked MSR access error: WRMSR to 0x11b (tried to write 0x0000000000000000)
Call Trace:
<IRQ>
? amd_threshold_interrupt+0x209/0x220
smp_threshold_interrupt+0x1b/0x40
threshold_interrupt+0x89/0x90
Use msr_stat instead which has the MSR address.
Fixes: 37d43acfd79f ("x86/mce/AMD: Redo error logging from APIC LVT interrupt
handlers")
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
Cc: Tony Luck <tony.l...@intel.com>
Cc: linux-edac <linux-e...@vger.kernel.org>
Cc: x86-ml <x...@kernel.org>
Link:
http://lkml.kernel.org/r/1495658507-7413-1-git-send-email-yazen.ghan...@amd.com
Signed-off-by: Borislav Petkov <b...@suse.de>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c
b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index d00f299f2ada..d11f94e8e68a 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -815,7 +815,7 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32
msr_addr, u64 misc)
__log_error(bank, status, addr, misc);
- wrmsrl(status, 0);
+ wrmsrl(msr_stat, 0);
return status & MCI_STATUS_DEFERRED;
}
--
2.13.0
