From: Kan Liang <[email protected]>
An earlier kernel patch allowed enabling PT and LBR at the same time on
Goldmont.
commit ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity
if the core supports it")
However, users still cannot use Intel PT and LBRs simultaneously. $
sudo perf record -e cycles,intel_pt//u -b -- sleep 1 Error: PMU
Hardware doesn't support sampling/overflow-interrupts.
PT implicitly adds dummy event in perf tool. dummy event is software
event which doesn't support LBR.
Always setting no branch for dummy event in Intel PT.
Signed-off-by: Kan Liang <[email protected]>
Acked-by: Jiri Olsa <[email protected]>
Cc: Adrian Hunter <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Andi Kleen <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
---
tools/perf/arch/x86/util/intel-pt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/perf/arch/x86/util/intel-pt.c
b/tools/perf/arch/x86/util/intel-pt.c
index 4a461e8ae326..db0ba8caf5a2 100644
--- a/tools/perf/arch/x86/util/intel-pt.c
+++ b/tools/perf/arch/x86/util/intel-pt.c
@@ -701,6 +701,7 @@ static int intel_pt_recording_options(struct
auxtrace_record *itr,
perf_evsel__set_sample_bit(switch_evsel, TID);
perf_evsel__set_sample_bit(switch_evsel, TIME);
perf_evsel__set_sample_bit(switch_evsel, CPU);
+ perf_evsel__reset_sample_bit(switch_evsel,
BRANCH_STACK);
opts->record_switch_events = false;
ptr->have_sched_switch = 3;
@@ -762,6 +763,7 @@ static int intel_pt_recording_options(struct
auxtrace_record *itr,
/* And the CPU for switch events */
perf_evsel__set_sample_bit(tracking_evsel, CPU);
}
+ perf_evsel__reset_sample_bit(tracking_evsel, BRANCH_STACK);
}
/*
--
2.9.4
