[PATCH v2 1/6] devicetree: Extend synopsys ddrc binding for Xilinx ZynqMP

[Michal Simek]

Add ZynqMP support to Synopsys memory controller.

Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---

Changes in v2:
- New patch in this series

 .../devicetree/bindings/memory-controllers/synopsys.txt    | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt 
b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
index a43d26d41e04..08c058d5ad76 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -5,11 +5,23 @@ configuration. The ECC controller corrects one bit error and 
detects
 two bit errors.
 
 Required properties:
- - compatible: Should be 'xlnx,zynq-ddrc-a05'
+ - compatible: Should be 'xlnx,zynq-ddrc-a05' for Zynq
+              and 'xlnx,zynqmp-ddrc-2.40a' for ZynqMP
  - reg: Base address and size of the controllers memory area
+ - interrupt-parent: Should be core interrupt controller
+                    valid for ZynqMP DDR Controller
+ - interrupts: Property with a value describing the interrupt number
+              valid for ZynqMP DDR Controller
 
 Example:
        memory-controller@f8006000 {
                compatible = "xlnx,zynq-ddrc-a05";
                reg = <0xf8006000 0x1000>;
        };
+
+       mc: memory-controller@fd070000 {
+               compatible = "xlnx,zynqmp-ddrc-2.40a";
+               reg = <0x0 0xfd070000 0x0 0x30000>;
+               interrupt-parent = <&gic>;
+               interrupts = <0 112 4>;
+       };
-- 
1.9.1