Re: [PATCH] mips: Fix using smp_processor_id() when preemptible

[Marcin Nowakowski]

Hi Corey,

This has already been fixed here:
https://git.linux-mips.org/cgit/ralf/upstream-sfr.git/commit/?id=21da5332327b6d183bd93336ecf29c70bc609b7b

https://git.linux-mips.org/cgit/ralf/upstream-sfr.git/commit/?id=735302665c353d6756e7fa2a2cf41b039299f732

Marcin

On 09.08.2017 23:25, miny...@acm.org wrote:

From: Corey Minyard <cminy...@mvista.com>

I was getting the following:

BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1
caller is pcibios_set_cache_line_size+0x10/0x58

pcibios_set_cache_line_size() used current_cpu_data outside of
an unpreemptible context.

Signed-off-by: Corey Minyard <cminy...@mvista.com>
---
  arch/mips/pci/pci.c | 5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index bd67ac7..afd2f8a 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -28,9 +28,11 @@ EXPORT_SYMBOL(PCIBIOS_MIN_MEM);

static int __init pcibios_set_cache_line_size(void)

  {
-       struct cpuinfo_mips *c = &current_cpu_data;
+       struct cpuinfo_mips *c;
        unsigned int lsize;

+ preempt_disable();

+       c = &current_cpu_data;
        /*
         * Set PCI cacheline size to that of the highest level in the
         * cache hierarchy.
@@ -38,6 +40,7 @@ static int __init pcibios_set_cache_line_size(void)
        lsize = c->dcache.linesz;
        lsize = c->scache.linesz ? : lsize;
        lsize = c->tcache.linesz ? : lsize;
+       preempt_enable();

BUG_ON(!lsize);