On Mon, Aug 07, 2017 at 01:46:41PM +1200, Chris Packham wrote:
> Some integrated Armada XP SoCs use a reduced pin count so the width of
> the SDRAM interface is smaller than the traditional discrete SoCs. This
> means that the definition of "full" and "half" width is further reduced.
>
> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
> ---
> drivers/edac/armada_xp_edac.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
> index 68e88b180928..d8edcaac87c0 100644
> --- a/drivers/edac/armada_xp_edac.c
> +++ b/drivers/edac/armada_xp_edac.c
> @@ -350,6 +350,9 @@ static int armada_xp_mc_edac_probe(struct platform_device
> *pdev)
> if (armada_xp_mc_edac_read_config(mci))
> return -EINVAL;
>
> + if (of_property_read_bool(pdev->dev.of_node, "marvell,reduced-width"))
> + drvdata->width /= 2;
If the compiler doesn't already convert it to a shift on ARM, you
probably should do
>>= 1;
here, just in case.
With that you can add my
Acked-by: Borislav Petkov <b...@suse.de>
and route it through an ARM tree.
Thx.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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