On Wed, Aug 23, 2017 at 11:13:04PM +0800, icen...@aosc.io wrote: > 在 2017-08-23 22:35，Maxime Ripard 写道： > > On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote: > > > > > + reg = <0x01c0f000 0x1000>; > > > > > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; > > > > > + clock-names = "ahb", "mmc"; > > > > > + resets = <&ccu RST_BUS_MMC0>; > > > > > + reset-names = "ahb"; > > > > > + pinctrl-0 = <&mmc0_pins>; > > > > > + pinctrl-names = "default"; > > > > > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > > > > > + max-frequency = <150000000>; > > > > > > > > have you tested that frequency? > > > > > > I think the frequency should be kept here, although my cards cannot > > > reach this frequency. > > > > > > The numbers are same as the corresponding controllers in A64. > > > > > > Maybe I should add a comment saying it's educated guess? > > > > I'd rather have it tested by someone, and then add the proper > > frequencies. It took quite a while to figure out how these modes were > > supposed to be working on the A64, so it's not obvious that they're > > just going to work. > > Should I add my results here? > > MMC0: 25MHz > MMC1: 50MHz > MMC2: 52MHz > MMC3: not wired :-( > > I think it's conservative enough and works well ;-)
And that's my point. You didn't test HS200, SDR50 or SDR104 for
example. So you have no idea whether the frequencies from 50MHz to
150MHz are actually working or not.
>
> >
> > > > > + gic: interrupt-controller@1c81000 {
> > > > > + compatible = "arm,gic-400";
> > > > > + reg = <0x01c81000 0x1000>,
> > > > > + <0x01c82000 0x1000>,
> > > > > + <0x01c84000 0x2000>,
> > > > > + <0x01c86000 0x2000>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <3>;
> > > > > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4)
> > > > > |
> > > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + timer {
> > > > > + compatible = "arm,armv7-timer";
> > > > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> > > > > IRQ_TYPE_LEVEL_LOW)>;
> > > >
> > > > Those masks are wrong.
> > >
> > > I compared it with other sun8i SoCs' device tree.
> > >
> > > Where's wrong?
> >
> > It's supposed to be a mask of the CPUs in your system. Since you just
> > have one of them, it shouldn't be 4.
>
> R40 has 4 cores...
>
> Or I didn't understand this?
Gah, sorry, I mistook this for the V3s for some reason...
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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