On Thu 2017-08-31 07:03:11, Stafford Horne wrote: > From: Stefan Kristiansson <[email protected]> > > Simple enough to be compatible with simulation environments, > such as verilated systems, QEMU and other targets supporting OpenRISC > SMP. This also supports our base FPGA SoC's if the cpu frequency is > upped to 50Mhz. > > Signed-off-by: Stefan Kristiansson <[email protected]> > [[email protected]: Added defconfig] > Signed-off-by: Stafford Horne <[email protected]> > --- > arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++ > arch/openrisc/configs/simple_smp_defconfig | 66 > ++++++++++++++++++++++++++++++ > 2 files changed, 124 insertions(+) > create mode 100644 arch/openrisc/boot/dts/simple_smp.dts > create mode 100644 arch/openrisc/configs/simple_smp_defconfig > > diff --git a/arch/openrisc/boot/dts/simple_smp.dts > b/arch/openrisc/boot/dts/simple_smp.dts > new file mode 100644 > index 000000000000..47c54101baae > --- /dev/null > +++ b/arch/openrisc/boot/dts/simple_smp.dts > @@ -0,0 +1,58 @@ > +/dts-v1/; > +/ { > + compatible = "opencores,or1ksim";
You may want to add some comment on top, explaining what this is... and perhaps link to some page documenting how to set up qemu/FPGAs? -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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