GPLL0 uses 4 bits post divider which should be specified in clock driver structure.
Signed-off-by: Abhishek Sahu <[email protected]> --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 0f735d3..f9b6d51 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -82,6 +82,7 @@ enum { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x21000, + .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_names = (const char *[]){ -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
