On Thu, Oct 05, 2017 at 03:48:53PM +0100, Ed Blake wrote: > On 04/10/17 15:03, James Hogan wrote: > > Hi Ed, > > > > On Mon, Oct 02, 2017 at 10:55:59AM +0100, Ed Blake wrote: > >> Pass on peripheral (RTC/IR/WD) irq masks and unmasks to the parent > >> interrupt controller, as well as setting / clearing the relevant bits > >> in the IRQ_ROUTE register. > >> > >> Clearing bits in the IRQ_ROUTE register will prevent future interrupts > >> from being passed on to the parent, but won't mask an existing > >> interrupt which has already made it to the parent. > > Is it an edge or level sensitive interrupt from the PDC? > > It's level triggered. > > > I'm a little rusty on the IRQ subsystem TBH, but if edge sensitive I > > would have expected the parent interrupt to be acked/cleared by the > > parent handler. > > > > And if level sensitive I would have expected the deasserted parent > > interrupt to be masked by the parent handler, and immediately cleared > > upon rerouting. > > > > Maybe you can clarify whats going on here. > > I'm not sure how this is supposed to work, but the issue seems to be > that without this patch the parent irq isn't being masked. This is > causing the parent handler (MIPS GIC in this case) to be called > continuously. This leads to the PDC irq being masked each time, but not > the parent irq. This is the callstack: > > "irq-imgpdc.c"::perip_irq_mask > mask_ack_irq > handle_level_irq > generic_handle_irq_desc > generic_handle_irq > generic_handle_irq_desc > generic_handle_irq > gic_handle_shared_int > gic_handle_local_int > "irq-mips-gic.c"::gic_irq_dispatch > generic_handle_irq_desc > generic_handle_irq > do_IRQ > plat_irq_dispatch()
Right, yeh it shouldn't technically be masked by the parent (contrary to what I said above) because its a chained handler, i.e. as far as the kernel knows there could be other IRQs coming through that GIC pin that would also get masked. (though IIRC the perip IRQs can wake, but then they go straight out to separate dedicated IRQ pins into the main IRQ chip, i.e. the GIC in this case). I think its worth understanding the root cause here though. Disabling routing of an IRQ fundamentally should deassert it. Is it an actual hardware bug that has reached silicon? Cheers James
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